This invention concerns a semiconductor integrated circuit device and a manufacturing technique therefor and, more in particular, it relates a technique effective to application to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
Memory cells of DRAM are generally located at intersection between each of a plurality of word lines and each of a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. One memory cell is constituted with one MISFET (Metal Insulator Semiconductor Field Effect Transistor) for selecting the cell and one information storage capacitance device (capacitor) connected in series with the MISFET.
The memory cell selecting MISFET is formed in a active region surrounded at the periphery thereof with a device isolation region and mainly comprises a gate insulating film, a gate electrode constituted integrally with a word line and a pair of semiconductor regions constituting the source and drain. Memory cell selecting MISFETs are usually formed by two in one active region and one of the source and drain (semiconductor region) of the two MISFET is made in common at the central portion of the active region.
The bit lines are disposed over the memory cell selecting MISFET and connected electrically through a contact hole in which a plug is buried with one of the source and drain (semiconductor region) (a semiconductor region in common with two MISFETs) Further, the information storage capacitance device is disposed over the bit line and electrically connected in the same manner through a contact hole in which a plug comprising polycrystal silicon or the like is buried with the other of the source and drain (semiconductor region) of the memory cell selecting MISFET.
As described above, DRAM in recent years adopts a sterical structure in which the information storage capacitance device is disposed over the bit line as a countermeasure for coping with reduction in the stored charge amount in accordance with the refinement of the memory cell. However, in the case of larger capacity DRAM of 256 Mbits or more in which the memory cell is to be refined further, it is considered difficult to cope with the reduction of the stored charge amount by merely making the information storage capacitance device sterical.
Then, it has been studied to adopt high dielectric (ferroelectric) materials such as tantalum oxide (Ta2O5), strontium titanate (STO) and barium strontium titanate (BST) as the dielectric film for the information storage capacitance device. This is because the relative dielectric constant is as high as about 40 in tantalum oxide and about 200 to 500 in STO and BST, so that remarkable increase in the stored charge amount can be expected in the case of using the high (ferro) dielectric material as the dielectric film compared with the case of using silicon nitride (relative dielectric constant=7 to 8) as the dielectric film.
However, since such high (ferro) dielectric materials can not provide high relative dielectric constant by merely being formed as films and show large leak current in the films, it is necessary to improve crystallization and film quality by applying a heat treatment in an oxygen atmosphere at 750xc2x0 C. or higher after film deposition. Accordingly, in the case of using the high (ferro) dielectric material for the dielectric film of the information storage capacitance device, the heat treatment at high temperature results in a problem of fluctuation in the characteristics of MISFET.
In view of the above, when the high (ferro) dielectric material is used for the dielectric film, a platinum group metal such as Ru (ruthenium), Pt (platinum) or Ir (iridium) is used for the lower electrode as the underlayer. When the high (ferro) dielectric film is deposited on the surface of the metal described above, since crystallization of film and improvement of the film quality can be obtained by a heat treatment at a low temperature such as 650xc2x0 C. to 600xc2x0 C. which is lower by 100xc2x0 C. or more than the usual heat treatment, the amount of heat treatment in the entire manufacturing steps can be decreased to prevent fluctuation in the characteristics of MISFET.
On the other hand, when the platinum group metal as described above is used for the lower electrode material, since this is an easily oxygen permeable material, when a heat treatment is conducted in an oxygen atmosphere after deposition of a high (ferro) dielectric film on the surface of the lower electrode, oxygen permeates through the high (ferro) dielectric film and the lower electrode and the silicon plug therebelow to bring about a problem that the platinum metal and the silicon are reacted to form an undesired metal silicide layer at the boundary between both of them. As a countermeasure, it has been proposed to form a barrier layer for preventing reaction between them between the lower electrode comprising the platinum group metal and the silicon plug.
Japanese Published Unexamined Patent Application Hei 10(1998)-79481 proposes a conductive layer containing a high melting metal such as Ti (titanium), W (tungsten), Ta (tantalum), Co (cobalt) or Mo (molybdenum), silicon and nitrogen (metal silicon nitride layer) as a barrier layer for preventing a disadvantage that the platinum group metal and silicon diffuse to each other to form a metal silicide layer or, further, the metal silicide layer is oxidized to form a silicon oxide layer of low dielectric constant by a heat treatment at 700 to 800xc2x0 C. upon reflow and flattening of a silicon oxide film. It is described that the barrier layer is preferably formed by lamination of a first layer containing columnar crystal or amorphous and a second layer containing granular crystals. Further, it is also described that a layer containing Ti is preferably formed between the barrier layer and the silicon plug for improving adhesion between them.
Japanese Published Unexamined Patent Application Hei 10(1998)-209394 points out a problem upon forming a lower electrode over a contact hole in which a silicon plug is buried that when mask misalignment is caused between them, the dielectric film formed over the lower electrode and the silicon plug below the lower electrode are in contact with each other to result in reaction between oxygen in the dielectric film and silicon to form a silicon oxide layer at high resistance, or the dielectric film lacks in oxygen to increase leak current. Then, this publication discloses a technique of providing a barrier film comprising silicon nitride between the dielectric film and the silicon plug as a countermeasure.
Japanese Published Unexamined Patent Application Hei 11(1999)-307736 concerns a ferroelectric memory and discloses a technique of forming a tantalum silicon nitride (TaSiN) film as a diffusion barrier layer over the silicon plug and forming an Ir film as an oxygen inhibition film over the diffusion barrier layer upon forming a capacitance device comprising a lower electrode comprising an iridium oxide (IrOx), a dielectric film comprising a dielectric material such as PZT (lead zirconate titanate) and an upper electrode comprising a platinum group metal such as Pt.
As described above, in the prior art, when a lower electrode comprising a platinum group metal is formed over a contact hole in which a silicon plug is buried and then a high (ferro) dielectric film is formed over the lower electrode and a heat treatment is conducted, undesired reaction between the platinum group metal and the silicon plug is prevented by previously forming a barrier layer over the silicon plug.
However, as the size of the memory cell is further refined, misalignment occurs inevitably between the lower electrode and the contact hole therebelow and the barrier layer in the contact hole may sometimes be etched upon patterning the lower electrode to expose the surface of the silicon plug. In this case, since a portion of the high (ferro) dielectric film formed over the lower electrode is in direct contact with the silicon plug, it results in a problem that the insulation break down voltage of the dielectric film is lowered to increase the leak current.
Further, as a result of the study made by the present inventors, it has been found a problem that when a barrier layer is formed over the silicon plug, and a heat treatment is conducted to the high (ferro) dielectric film in a high temperature oxygen atmosphere, oxygen permeating through the lower electrode oxidizes the barrier layer itself to form an oxide layer of high resistance and low dielectric constant.
Further, the present inventors have studied a process of depositing a thick silicon oxide film over a contact hole in which a silicon plug is buried, then etching the silicon oxide film to form a deep groove reaching the surface of the silicon plug and depositing a platinum group metal film on the inner wall of the groove to form a lower electrode, and have found a problem that peeling may sometimes be caused between the lower electrode and the silicon oxide film in the course of the production steps because of less adhesion between the platinum group metal film and the silicon oxide film.
This invention intends to provide a technique capable of preventing disadvantage that a barrier layer in the contact hole is etched to expose the surface of a silicon plug upon patterning a lower electrode, in a case where the size of the memory cell is further refined and misalignment occur inevitably between the lower electrode of a capacitance device and a contact hole therebelow.
This invention further intends to provide a technique capable of preventing disadvantage that an oxide layer of high resistance and low dielectric constant is formed upon heat treatment of a dielectric film formed over the lower electrode of a capacitance device in an oxygen atmosphere by the oxidation of the barrier layer itself with oxygen that permeates the lower electrode.
This invention further intends to provide a technique capable of improving adhesion between a platinum group metal film constituting the lower electrode for a capacitance device and a silicon oxide film.
This invention further provides a technique capable of ensuring a desired stored charge amount value even in a case of reducing the size of a memory cell, by increasing the surface area of a capacitance device and making the dielectric constant of the dielectric film higher.
The foregoing and other objects as well as novel features of this invention will become apparent by reading the descriptions of the present specification and appended drawings.
Among the inventions disclosed in this application, outlines of typical inventions are to be briefly explained as below.
In a semiconductor integrated circuit device according to this invention, a capacitance device constituted with a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed on a main surface of a semiconductor substrate, in which a first semiconductor region formed in the semiconductor substrate and the first electrode of the capacitance device are electrically connected by way of a silicon plug inside a first contact hole formed in a first insulating film over the first semiconductor region, and in which
a metal silicide layer is formed on the surface of the silicon plug, and at least one of a metal silicon nitride layer or a metal silicon oxynitride layer is formed on the surface of the metal silicide layer.
In a semiconductor integrated circuit device according to this invention, a capacitance device constituted with a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed on a main surface of a semiconductor substrate, in which a first semiconductor region formed in the semiconductor substrate and the first electrode of the capacitance device are electrically connected by way of a silicon plug inside a second contact hole formed in a second insulating film over the first semiconductor region, and a metal plug inside a first contact hole formed in a first insulating film over the second insulating film and in which
a metal silicide layer is formed on the surface of the silicon plug, and at least one of a metal silicon nitride layer or a metal silicon oxynitride layer is formed on the surface of the metal silicide layer.
A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:
(a) forming a first insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a first contact hole to the first insulating film over the first semiconductor region,
(b) forming a silicon plug inside the first contact hole,
(c) forming a third insulating film over the first insulating film, and then etching the third insulating film over the first contact hole, thereby forming a groove in which the surface of the silicon plug is exposed at the bottom thereof,
(d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,
(e) forming a first electrode for the capacitance device comprising a first metal inside the groove, and electrically connecting the first electrode and the first semiconductor region through the first contact hole,
(f) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and
(g) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.
A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:
(a) forming a second insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a second contact hole to the second insulating film over the first semiconductor region,
(b) forming a silicon plug in the second contact hole,
(c) forming a first insulating film over the second insulating film, and then etching the first insulating film over the second contact hole thereby forming a first contact hole in which the surface of the silicon plug is exposed at the bottom thereof,
(d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,
(e) forming a metal plug inside the first contact hole,
(f) forming a third insulating film over the first insulating film and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the metal plug is exposed at the bottom thereof,
(g) forming a first electrode comprising a first metal for a capacitance device inside the groove, and electrically connecting the first electrode and the first semiconductor region through the first contact hole and the second contact hole,
(h) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and
(i) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.
A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:
(a) forming a first insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a first contact hole to the first insulating film over the first semiconductor region,
(b) forming a silicon plug in the first contact hole,
(c) forming a third insulating film over the first insulating film, and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the silicon plug is exposed at the bottom thereof,
(d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,
(e) a step forming a first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove,
(f) removing the third insulating film by etching to form a columnar first electrode comprising the columnar first metal for the capacitance device over the first contact hole and electrically connecting the first electrode and the first semiconductor region by way of the first contact hole,
(g) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and
(h) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.
A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:
(a) forming a second insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a second contact hole to the second insulating film over the first semiconductor region,
(b) forming a silicon plug in the second contact hole,
(c) forming a first insulating film over the second insulating film, and then etching the first insulating film over the second contact hole thereby forming a first contact hole in which the surface of the silicon plug is exposed at the bottom of thereof,
(d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,
(e) forming a metal plug inside the first contact hole,
(f) forming a third insulating film over the first insulating film and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the metal plug is exposed at the bottom thereof,
(g) forming a first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove,
(h) etching to remove the third insulating film to form a columnar first electrode comprising the first metal film for capacitance device over the first contact hole, and electrically connecting the fist electrode and the first semiconductor region through the first contact hole and the second contact hole,
(i) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and
(j) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.